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| SSG6680 11.5A, 30V,RDS(ON) 11m[ Elektronische Bauelemente N-Channel Enhancement Mode Power Mos.FET RoHS Compliant Product SOP-8 Description The SSG6680 provide the designer with the best combination of fast switching, ruggedized device design, low on-resistance and cost-effectiveness. The SOP-8 is universally preferred for all commercial industrial surface mount application and suited for low voltage applications such as DC/DC converters. 0.35 0.49 1.27Typ. 4.80 5.00 0.100.25 6.20 5.80 0.25 0.40 0.90 0.19 0.25 45 o 0.375 REF 3.80 4.00 Features * Surface Mount Package * High Vgs Max. Rating Voltage * Low On-Resistance D 8 D 7 D 6 D 5 0 o 8 o 1.35 1.75 Dimensions in millimeters D 6680SC Date Code G 1 S 2 S 3 S 4 G S Absolute Maximum Ratings Parameter Drain-Source Voltage Gate-Source Voltage Continuous Drain Current Continuous Drain Current Pulsed Drain Current 1 3 3 Symbol VDS VGS ID@TA=25 C ID@TA=70 C IDM PD@TA=25 C o o o Ratings 30 25 11.5 9.5 50 2.5 0.02 Unit V V A A A W W/ C o o Total Power Dissipation Linear Derating Factor Operating Junction and Storage Temperature Range Tj, Tstg -55~+150 C Thermal Data Parameter Thermal Resistance Junction-ambient 3 Symbol Max. Rthj-a Ratings 50 o Unit C /W http://www.SeCoSGmbH.com/ Any changing of specification will not be informed individual 01-Jun-2002 Rev. A Page 1 of 5 SSG6680 11.5A, 30V,RDS(ON) 11m[ Elektronische Bauelemente N-Channel Enhancement Mode Power Mos.FET Electrical Characteristics( Tj=25 oC Unless otherwise specified) Parameter Drain-Source Breakdown Voltage Breakdown Voltage Temp. Coefficient Gate Threshold Voltage Gate-Source Leakage Current Drain-Source Leakage Current (Tj=25oC) Drain-Source Leakage Current (Tj=70oC) Static Drain-Source On-Resistance2 Symbol BVDSS BVDS/ Tj VGS(th) IGSS IDSS Min. 30 _ Typ. _ Max. _ _ Unit V V/ oC V nA uA uA Test Condition VGS=0V, ID=250uA Reference to 25oC, ID=1mA VDS=VGS, ID=250uA VGS= 25A VDS=30V,VGS=0 VDS=24V,VGS=0 VGS=10V, ID=11.5A VGS=4.5V, ID=9.5A 0.02 _ _ _ _ _ _ 1.0 _ _ _ _ 3.0 100 1 25 11 18 _ _ _ RDS(ON) Qg Qgs Qgd Td(ON) Tr Td(Off) Tf Ciss Coss Crss Gfs _ _ _ _ _ _ _ _ _ _ _ m[ Total Gate Charge 2 16.8 4.2 8 8.9 7.3 25.6 18.6 1450 285 180 30 Gate-Source Charge Gate-Drain ("Miller") Charge Turn-on Delay Time2 Rise Time Turn-off Delay Time Fall Time Input Capacitance Output Capacitance Reverse Transfer Capacitance Forward Transconductance nC ID=11.5A VDS=15V VGS=5V _ _ _ _ VDD=15V ID=1A nS VGS=10V RG=5.5 [ RD=10 [ _ _ _ pF VGS=0V VDS=25V f=1.0MHz _ _ S VDS=15V, ID=11.5A Source-Drain Diode Parameter Forward On Voltage 2 Continuous Source Current (Body Diode) Symbol VDS Is Min. _ Typ. _ Max. 1.3 Unit V Test Condition IS=3.5A,VGS=0V,Tj=25 C VD=VG=0V, VS=1.3V o _ _ 1.92 A Notes: 1.Pulse width limited by Max. junction temperature 2.Pulse widthO 300us, dutycycleO2%. 3.Surface mounted on 1 inch2 copper pad of FR4 board; 125C/W when mounted on min. copper pad. http://www.SeCoSGmbH.com/ Any changing of specification will not be informed individual 01-Jun-2002 Rev. A Page 2 of 5 SSG6680 11.5A, 30V,RDS(ON) 11m[ Elektronische Bauelemente N-Channel Enhancement Mode Power Mos.FET Characteristics Curve Fig 1. Typical Output Characteristics Fig 2. Typical Output Characteristics Fig 3. On-Resistance v.s. Gate Voltage Fig 4. Normalized On-Resistance v.s. Junction Temperature Fig 5. Maximum Drain Current v.s. Case Temperature http://www.SeCoSGmbH.com/ 01-Jun-2002 Rev. A Fig 6. Type Power Dissipation Any changing of specification will not be informed individual Page 3 of 5 SSG6680 11.5A, 30V,RDS(ON) 11m[ Elektronische Bauelemente N-Channel Enhancement Mode Power Mos.FET Fig 7. Maximum Safe Operating Area Fig 8. Effective Transient Thermal Impedance Fig 9. Gate Charge Characteristics Fig 10. Typical Capacitance Characteristics Fig 11. Forward Characteristics of Reverse Diode http://www.SeCoSGmbH.com/ Fig 12. Gate Threshold Voltage v.s. Junction Temperature Any changing of specification will not be informed individual 01-Jun-2002 Rev. A Page 4 of 5 SSG6680 11.5A, 30V,RDS(ON) 11m[ Elektronische Bauelemente N-Channel Enhancement Mode Power Mos.FET Fig 13. Switching Time Circuit Fig 14. Switching Time Waveform Fig 15. Gate Charge Circuit Fig 16. Gate Charge Waveform http://www.SeCoSGmbH.com/ Any changing of specification will not be informed individual 01-Jun-2002 Rev. A Page 5 of 5 |
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